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      "content": "That's what I usually do but I was hoping for something with a bit less Vdd dependence ...\nHere say I make by 30 uA at 3.3V nominal. Voltage across nmos will be say ~ 1.5V so I have R = (3.3 - 1.5) / 30u = ~ 60k.  When going to 5V, the 1.5V drop is much less significant so I have 3.5V across resistor and not 1.8V anymore and I go to 58 uA. Simulating it's actually a bit worse than that and then if you had corners, you go even more off.\n\nSo I was hoping for something that at least reduces the Vdd dependence somewha.t",
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      "content": "And AFAICT the widlar source does nothing to help that.",
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      "content": "That's what I think I'll end up with.",
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      "content": "Bigger that I would have liked, but should be decent enough.",
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      "content": "or actually might use the same topology but in nmos, makes it a bit smaller.",
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      "content": "Stack mos diodes; tap resistor off that intermediate into a current mirror? You have headroom at these Vdd's",
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      "content": "Problem is solved. The above works.\nThis is a temp sweep from 15C to 50C (realistic operating range) with VDD from 3 to 5.  Typical corner. And this goes from 31uA to 37uA.\nSweeping across all transitor and resistor corners and vdd and temp, I get from 22uA to 55uA which is good enough for this application.",
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      "content": "Yay",
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